1. Field of the Invention
The invention relates to a method for fabricating a semiconductor device and, for example, relates to a manufacturing method of a semiconductor device for forming a fine wire.
2. Related Art
In recent years, with ever higher degrees of integration and higher performance of semiconductor integrated circuits (LSI), new microprocessing technologies have been developed. In particular, to achieve an ever faster speed of LSI, there has been a growing trend recently to replace the conventional wire material of aluminum (Al) alloys with copper (Cu) or Cu alloys (hereinafter, called Cu together) having lower resistance. Since it is difficult to apply the dry etching method, which is frequently used for forming an Al alloy wire, to Cu for microprocessing, the so-called damascene process is mainly adopted for Cu, in which a Cu film is deposited onto a dielectric film to which groove processing has been provided and then the Cu film is removed except in portions where the Cu film is embedded in a groove by chemical-mechanical polishing (CMP) to form an embedded wire. The Cu film is generally formed, after forming a thin seed layer by a sputter processor the like, into a laminated film having a thickness of several hundred nanometers by the electro-plating method.
Recently, the use of a low dielectric constant film (low-k film) having a low relative dielectric constant as an inter-level dielectric is studied. That is, an attempt is made to reduce parasitic capacitance between wires by using a low dielectric constant film (low-k film) whose relative dielectric constant k is 3 or less, instead of silicon oxide (SiO2) whose relative dielectric constant k is about 4.2. Then, a barrier metal film of titanium nitride (TiN) or the like is first formed on a sidewall or at a bottom of a groove and then Cu is embedded to prevent diffusion of Cu into the low-k film.
To further reduce parasitic capacitance between wires, a technology to form an air gap and the like has also been attempted. For example, a sidewall layer made of amorphous carbon fluorine is first formed on sidewalls of a wire groove. Then, after forming a barrier metal film and a Cu film, the sidewall layer is removed to form an air gap (See, for example, Japanese Unexamined Patent Application Publication No. 2003-163266).
Though reduced parasitic capacitance between wires and lower resistance of wires have been promoted, as described above, it is becoming increasingly difficult to embed Cu in a groove with ever narrower width of the groove. Currently, Cu can be embedded in a groove by the damascene process up to the wiring width of about 50 nm at an applicable level of mass production. However, with ever higher degrees of integration and higher performance of LSI, development of a still finer wire is demanded. Thus, development of a technology to embedded Cu in a still narrower wiring groove is urgently necessary. Such a technology to improve embedding properties of Cu has not been developed.